SAR ADC design consideration

A typical SAR ADC consists of three components: DAC, comparator, and SAR logic. It has become a superior ADC topology with a good tradeoff between power consumption, speed, and resolution.

Many studies have been made in several aspects. The first one is related to DAC topology. There are three main structures: switched resistors network, switched current sources network, and switched capacitors network. Among them, two main categories of Switched-capacitor DACs are charging-sharing and charge-redistribution. Many scholars made efforts on proposing and discussing different types of SC architectures and switching algorithms to improve the efficiency, linearity, accuracy and power consumption.

The second one is related to comparator design. The dynamic comparator has been dominant for good power efficiency. Inverter-based and time-based comparator have been popular recently.

The third one is related to SAR logic. The switching method can be accounted for this aspect. The SAR logic also plays a role in outputting digital codes. When the CMOS processing keeps scaling, the digital power of the SAR logic becomes more dominant in the whole SAR ADC. So to find a better way of saving digital power could be a promising research direction.

In addition, people also study the non-binary search, binary search with redundancy, and calibration method to optimize the linearity, mismatch and gain error issues for the SAR ADC architecture.




The SC DAC network doesn't consume static power so it is widely used for low power applications. Another reason is that SC network can be used as S/H circuit in the sampling phase.

In terms of SC DAC, many studies have been made on capacitor array topologies and switching methods. Some parameters like ADC linearity, energy efficiency, performance, and area are used to evaluate them.

The split capacitor topology is one of them, which aims to reduce the capacitor area. However, considering the capacitor mismatch, parasitic capacitance, kT/C noise, the split capacitor topology is more sensitive to parasitic effects, a larger unit capacitor must be used and in some cases can produce even larger total area than simply binary-weighted capacitor network.