QSPICE - Learn how to use QSpice from the beginning

# Start to use Qspice textbook circuit models from ASICedu.com - Make sure to install QSPICE and unzip the Qspice_CMOSedu.zip (link) - Launch QSPICE - Open a schematic using the 'open' icon in the toolbar - Navigate to the Qspice model folder extracted from Qspice_CMOSedu.zip - Select a schematic corresponding to a book figure - Run the simulation by clicking the 'Green' icon in the toolbar menu - The simulation results will automatically plot in another Qspice window - To display some other signals, voltage or current: 1. make sure the '.save all' spice code is used in the schematic; 2. Right click the plot panel and select 'Add Window' to create a new panel; 3. Right click the new panel and select 'Add Plot' in the new panel; 4. Pick the voltage or current you like to plot and then click 'OK'. (On the top of 'Compose Expression to Plot', many math functions can be used) --- > Launch QSPICE --- > Open a new QSPICE schematic --- > Select the textbook circuit model --- > Run the simulation --- > Plot simulation results and Create a new window panel in the plot (Right click the current plot panel)  --- > Add plot in the new panel (Right click the new panel)  --- > Select another signal to plot in new panel and function table listed in the 'New Expression window'  --- > Final Simulation Result Plot 

Matlab - Add reference line in a bode plot

# Add reference line in a bode plot Sometimes, adding a reference line can explain a lot in a plot. For PLL noise transfer functions, the reference noise transfer function has a low pass characteristic. The VCO noise transfer function has a high pass characteristic. The PLL bandwidth splits the noise plot into two regions: - phase noise of VCO dominates the high frequencies because its noise transfer function have no effect in this region - phase noise of references and phase detector dominates the low frequency region > noise transfer functions of the reference and VCO Therefore, it is useful to show the PLL bandwidth in the plot. New version Matlab provides a 'xline' function, vertical line with constant x-value, to plot a line in a plot. If you don't have the new version of Matlab, you can use another m function ([Link](https://wwem.lanzouq.com/iSonk1hpecmh)) to add a reference line. Example code is shown below:

Demo - IVerilog + GTKWave

--- # Summary - installation iverilog and gtkwave - run the digital demo block to check the tool flow - compile the code: - `iverilog -o DUT.out DUT.v tb_DUT.v` - run the executable file - `vvp DUT.out` - plot dumped *.vcd* data file (don't forget the put dumped code in testbench) - `gtkwave DUT.vcd` - different OS can use different ways to make the flow easier. Please send an email to ask for codes working on Windows or Linux. - Window OS: `.bat` file - Linux OS: `Makefile` --- ``` initial begin $ dumpfile("DUT.vcd"); //The name of the generated vcd file $ dumpvars(0, tb_DUT ); //The name of the tb module end ``` --- # Introduction [Icarus Verilog](https://github.com/steveicarus/iverilog)) is an open-source Verilog simulator with _some_ SystemVerilog support. I really like to use it for quick digital circuit design and simulation. Icarus Verilog compiles the Verilog source into a file that is executed by its simulator `vvp`. [GTKWave](http://gtkwave.sourceforge.net/) is a open-source waveform viewer/plot tool, which is excellent for plotting digital signals in the simulation. It supports to read and view LXT, LXT2, VZT, FST, and GHW files as well as standard Verilog VCD/EVCD files Many fresh engineers might not be familiar with Iverilog and GTKWave. After using it for many years, I wish I know it when I was in college so I'd like to give a quick tutorial for all new engineer students who like to try open-source digital tool. # Demo Example Basic 4-b counter is written in verilog. ``` /** * 4-bit counter */ module counter ( input clk, // posedge clock input clr, // synchronous clear input en, // enable: active high to increment output [3:0] cnt // counter value ); reg [3:0] cnt_reg, cnt_next; assign cnt = cnt_reg; always @(*) begin cnt_next = cnt_reg; if (clr) begin cnt_next = 4'd0; end else if (en) begin cnt_next = cnt_reg + 1; end end always @(posedge clk) begin cnt_reg <= cnt_next; end endmodule ``` The simple counter testbench ``` `timescale 1ns/100ps // 1 ns time unit, 100 ps resolution module tb_counter; reg clk; always #5 clk = !clk; reg clr, en; wire [3:0] cnt; counter counter_0 ( .clk(clk), .clr(clr), .en(en), .cnt(cnt) ); integer i; initial begin // create a VCD waveform dump called "tb_counter.vcd" // dump variable changes in the testbench // and all modules under it $dumpfile("counter.vcd"); $dumpvars(0, tb_counter); end initial begin $monitor("t=%-4d: cnt = %d", $time, cnt); clk = 0; clr = 1; en = 0; @(negedge clk); clr = 0; en = 1; for (i = 0; i < 64; i = i + 1) begin @(negedge clk); end $finish(); end endmodule ``` The function `$dumpfile()` and `$dumpvars()` are to output vcd file for plotting data. # Simulation Flow ## compile and run iverilog compiles the source modules to produce files for vvp. ``` iverilog -o tb_counter.out counter.v tb_counter.v vvp counter.out ``` Makefile is used to speed up in Linux. ``` TOP = test_counter SRC = counter.v TEST_SRC= tb_counter.v BIN = $(TOP).vvp $(BIN): $(SRC) $(TEST_SRC) iverilog -o $(BIN) -s $(TOP) $(SRC) $(TEST_SRC) .PHONY: all clean test all: $(BIN) test: $(BIN) vvp $(BIN) clean: rm -f *.vvp *.vcd ``` For better usage, I have an updated Makefile. Please send me an email to get a copy of it. ## Plot Data GTKWave is to open vcd files and to plot signals. ``` gtkwave counter.vcd ``` # More about Iverilog ## parameter `-o` set the name of compiling output file: `iveirlog test.v -o test.out` ## parameter `-y` set the project folder or design folder: `iverilog -y $DIR/demo demo_tb.v` ## parameter `-tvhdl` convert verilog to VHDL: `iverilog -tvhdl -o output_file.vhd in_file.vhd`

Creating Device Sue Symbols for SkyWater SKY130 Process

I customized device symbols for using CppSim/Sue tool to run skywater sky130 process.

CppSim is an open-source, wonderful and powerful EDA tool. I like to use it for running some simulations. In order to design circuits in real PDK, I start this interesting project.

Now I listed the following symbols ready to use.

 

 

The following demo is shown to demonstrate a simple circuit simulation flow by using sue+ngspice+sky130_pdk.

 

Cadence QRC notes

Cadence QRC is the parasitic RCL (resistance, capacitance, and inductance) extraction tool which is valuable and powerful to help IC designers to complete both digital- and transistor-level circuit design and assure on-time tapeout.

Correct QRC Tips

Several useful tips can assure engineers to run efficiently and faultless:

1. Pass the LVS check before proceeding

   

2. Select the correct Setup Dir to the PDK QRC folder if RuleSet is displayed 'NONE'. (different QRC setup dir: RC, RC_type, RC_max, RC_min, etc. ) In typical, select RC_max QRC folder to get the worse case result.

3. Set different Temperature in Extraction option. In the PVT simulation, engineers usually are asked to run TT 27C, FF -40C, SS 125C for pre- and post-simulation. So several extraction views are generated like av_extracted_rcmax_27, av_extract_rcmax_125, av_extract_rcmax_n40.

4. Set Ref Node to be the correct ground PIN of the design block

5. Set Extraction Type to be RC or C only typically

6. Enter all PIN names of VDDs and Grounds to the Power Nets and Ground Nets in the Filtering option

 

Final Correct Window of QRC extraction

 

Parasitic back-annotation

After getting the parasitic extraction cell view, check/review the parasitics in schematic view could help engineers to understand which nodes have more parasitics.

Back-annotation tool can be launched in schematic window by clicking Launch ---> Plugins ---> Parasitics. In Setup Parasitics window as below, make sure select the correct view name and cell name. Then, press OK and go to Parasitics Menu to select Show Parasitics.

The original schematic displays the summation of capacitance in each node.

Post-simulation

Post-simulation process needs to create the 'config' view of the testbench cell and then select the extraction cell view of expected subcircuits or the whole top-level design.

In the New Configuration window, please use AMS temperate for mixed-signal circuit simulation, which means the testbench has some block in verilog/verilogams models.

In the expected checking circuit, select its extraction view. Better to update or recompute the hierarchy to proceed the simulation process.

Press Open to open the schematic editor with the config view and launch ADE L or ADE XL or ADE explorer to run the simulation.

Tips:

1. Select the design block and Press 'E' to check what is the current cell view. It should be matched to the view in the config window
2. always make sure that the word 'config' exists in the schematic editor window's name
3. update and recompute the hierarchy whenever the schematic is modified or check and saved

design procedure for ADPLL parameter determination

System design procedure for Type-II second-order ADPLL 

Reading the following reference, learn how to analyze the ADPLL. There is an error in calculating the resistor of the loop filter. It was corrected in the matlab code.

[1]

V. Kratyuk, P. K. Hanumolu, U.-K. Moon, and K. Mayaram, “A Design Procedure for All-Digital    Phase-Locked Loops Based on a Charge-Pump Phase-Locked-Loop Analogy,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 54, no. 3, pp. 247–251, Mar. 2007, doi: 10.1109/TCSII.2006.889443.

For better learning and understanding the publication, I created a mindmap reference and matlab code. 

• Mindmap Reference and Matlab code: Download Link (send email to me to ask for the password)

PFD gain calculation