capacitor consideration in switched-capacitor DACs

In the capacitor array of a switched-capacitor DAC, each capacitor can be expressed as below considering mismatch and parasitics;

where  is the parasitic capacitance related to the i-th capacitor and  is the mismatch equivalent capacitance affecting the unit capacitor. The effect of the parasitic capacitances can be considered deterministic, depending on layout inaccuracies, capacitor geometry, and wirings. On the contrary, the capacitance mismatch can be modeled as a Gaussian distribution of the unit capacitor value with a mean equal to the nominal capacitance, , and a standard deviation equal to 

where  being the Pelgrom mismatch coefficient, the unit capacitance, the area and the unit capacitance per area, respectively.

For example, if the Pelgrom mismatch coefficient is given as 0.43% um, for a 22fF unit capacitor with 3um x 3um area, the unit capacitance per area is 2.45fF/um^2 and the standard deviation is  0.02237fF.

Another important parasitic in the charge-redistribution array is the stray capacitance connected to the top-plate node of the array to a fixed voltage node. The parasitic capacitance causes a gain error in the converter characteristic but in some ADC topologies, it can also affect the converter nonlinearity.

The maximum standard deviation of the DNL in a conventional binary weighted array with single-ended input is

In order to get less than 1LSB DNL, the unit capacitor needs to be

Using the above parameters, a 10bit DAC needs to have a larger than 733fF unit capacitor to guarantee the DNL less than 1LSB.

Ref[1] mentioned that overall limitations and a suitable margin suggest using a unit capacitor in SC DACs to be larger than 40fF.

Hence, interesting research could study how the size of capacitors in DAC affects its linearity.

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[1] Design of an ultra-low power SA-ADC with medium/high resolution and speed written by Andrea Agnes, and et al.