Cadence QRC notes

Cadence QRC is the parasitic RCL (resistance, capacitance, and inductance) extraction tool which is valuable and powerful to help IC designers to complete both digital- and transistor-level circuit design and assure on-time tapeout.

Correct QRC Tips

Several useful tips can assure engineers to run efficiently and faultless:

1. Pass the LVS check before proceeding

   

2. Select the correct Setup Dir to the PDK QRC folder if RuleSet is displayed 'NONE'. (different QRC setup dir: RC, RC_type, RC_max, RC_min, etc. ) In typical, select RC_max QRC folder to get the worse case result.

3. Set different Temperature in Extraction option. In the PVT simulation, engineers usually are asked to run TT 27C, FF -40C, SS 125C for pre- and post-simulation. So several extraction views are generated like av_extracted_rcmax_27, av_extract_rcmax_125, av_extract_rcmax_n40.

4. Set Ref Node to be the correct ground PIN of the design block

5. Set Extraction Type to be RC or C only typically

6. Enter all PIN names of VDDs and Grounds to the Power Nets and Ground Nets in the Filtering option

 

Final Correct Window of QRC extraction

 

Parasitic back-annotation

After getting the parasitic extraction cell view, check/review the parasitics in schematic view could help engineers to understand which nodes have more parasitics.

Back-annotation tool can be launched in schematic window by clicking Launch ---> Plugins ---> Parasitics. In Setup Parasitics window as below, make sure select the correct view name and cell name. Then, press OK and go to Parasitics Menu to select Show Parasitics.

The original schematic displays the summation of capacitance in each node.

Post-simulation

Post-simulation process needs to create the 'config' view of the testbench cell and then select the extraction cell view of expected subcircuits or the whole top-level design.

In the New Configuration window, please use AMS temperate for mixed-signal circuit simulation, which means the testbench has some block in verilog/verilogams models.

In the expected checking circuit, select its extraction view. Better to update or recompute the hierarchy to proceed the simulation process.

Press Open to open the schematic editor with the config view and launch ADE L or ADE XL or ADE explorer to run the simulation.

Tips:

1. Select the design block and Press 'E' to check what is the current cell view. It should be matched to the view in the config window
2. always make sure that the word 'config' exists in the schematic editor window's name
3. update and recompute the hierarchy whenever the schematic is modified or check and saved

Additional cadence design libraries for IC design

Cadence provides many design libraries.

 

Cadence also provides "Customizing the Library Manager"

The actual method is quoted as below:

"At first, create a dummy directory with the name you want to give your combined library (kind of a kludge, but oh well).  Then edit your cds.lib and add 2 lines:

DEFINE <combinedLibName> <pathToDummyDirectoryYouCreatedAbove>

ASSIGN <combinedLibName> COMBINE <lib1> <lib2> ...

These lines need to go after all the lib1, lib2, etc. libraries are defined.

That's it.  Now when you open the Library Manager, you'll see your combined library name with a "+" sign next to it.  If you click on the combined library name, you'll see all the cells in all the libraries combined.  If you click the "+" sign, you can still access the libraries individually as usual. "

How to simulate setup time and hold time of any DFF in cadence tool

Setup time is defined as the minimum amount of time before the clock's active edge that the data must be stable for it to be latched correctly. Any violation may cause incorrect data to be captured, which is known as setup violation.

Hold time is defined as the minimum amount of time after the clock's active edge during which data must be stable. A violation in this case may cause incorrect data to be latched, which is known as a hold violation. Note that setup and hold time is measured with respect to the active clock edge only.

Many fresh engineers know the definition but they don't know how to simulate them. I wrote a tutorial summarizing previous works coming from excellent engineers. 

The tutorial discussed how to simulate the setup time and hold time of a DFF.

Tips to use cadence environment in Linux/Unix system

Make Nautilus (file manager) behave like a browser

Nautilus is the default file manager on the lab computers. You have likely noticed that, with the default settings, it spawns a new windows each time you open a folder. If you find this annoying, you can change its behavior with the following steps:

• Open the preferences dialogue (Edit->Preferences)
• Click on the behavior tab
• Tick the always open in browser windows option

Firefox profile lock (error message with "Firefox is currently running...")

Frequently, if you do not close firefox properly, it will give an error message next time you try to open it. To fix this problem, navigate to ~/.mozilla/firefox and look for a folder with a mix of numbers and letters followed by "Default User". In this folder, you will find an invisible file called .parentlock; delete this file and the problem should be fixed.

Locked Files in Cadence

If you try to open an old file and Cadence says you can't edit the file, it is because this file has become "locked." This usually happens as a result of Cadence crashing while the file was open.
To unlock the file, you need to search for and remove (using the rm command) a file that ends in ".cdslck". You will often have to look through directories and subdirectories to find this file, but look in directories that have the same name as the cellview in question. For example if you are having trouble opening the schematic in cellview "Inverter" in library "myLib" then you would go to the folder myLib/Inverter/ and look for all files ending in ".cdslck".
As an alternative to manually searching through the directories you can use the command (from the directory where you start cadence):

find . -name "*.cdslck"

Before you run this command close all open shcematics and layouts. Then simply remove all files that appear.
To remove all cdslck files, you can use the command rm together with searching(from the directory where you start cadence):

find . -name "*.cdslck" -exec rm -f {} \;

Reference: https://secure.engr.oregonstate.edu/wiki/ams/index.php/Cadence/TipsAndTricks#toc11

Set # of sig figs on schematic annotation

Sometimes the number of significant figures on schematic annotations (node voltages, for example) is very high and it becomes difficult to read. To fix this, type the following into the icfb window:
envSetVal("auCore.misc" "labelDigits" 'int 5)
Change the number 5 to your desired number of sig figs. To make this change permanent, add the line to your ~/.cdsenv file.

Set the default script/veriogA editor in Cadence to gedit

• Option 1: type the following in CIW command line

editor="gedit"

• Option 2: add the line to .cdsinit

editor="gedit"



Change Waveform Graph windows default settings

Add some of the following lines to .cdsenv file to change the window size, background/foreground color, font size, line thickness,and etc.

;width
viva.graphFrame width string "900"
;height
viva.graphFrame height string "700"
;background color
viva.rectGraph background string "white"
;foreground color
viva.rectGraph foreground string "black"
;axis font
viva.axis font string "Fixed [Misc],14,-1,5,50,0,0,0,0,0"
;marker font
viva.pointMarker font string "Fixed [Misc],14,-1,5,50,0,0,0,0,0"
viva.horizMarker font string "Fixed [Misc],14,-1,5,50,0,0,0,0,0"
viva.vertMarker font string "Fixed [Misc],14,-1,5,50,0,0,0,0,0"
viva.multiDeltaMarker font string "Fixed [Misc],14,-1,5,50,0,0,0,0,0"
viva.refPointMarker font string "Fixed [Misc],14,-1,5,50,0,0,0,0,0"
;line thickness
viva.trace lineThickness string "thick"

You may also use envSetVal to set the environment. For example, to set the background to white, type the following in the CIW window.

envSetVal(“viva.rectGraph” “background” 'string “white”)

Save operating point information over a DC sweep

You may notice that DC operating point information (gm, gds, etc.) does not get saved over a DC sweep. One way to work around this is to replicate the sweep using the parametric sweep tool. In some cases, however, this may constrain your simulation setup. If you simply want the op information to be saved for every point in a sweep, follow these directions:

• Make a new text file (saveop.scs, for example) in a directory to which you have read-write access.
• Add the following line to the file, replacing N0 with the name of the device whos operating point you wish to save:

save N0:oppoint

• Save the file. Return to your ADE window, navigate to Setup->Model Libraries; now the file you just made to the list.
• Run your simulation and find the saved data in the Results Browser (under the Tools menu in the ADE). You can also access the data with equations (i.e. getData("M0:vdsat" ?result 'dc)).
• You can, of course, have multiple lines in the file for multiple devices. For large simulations, consider saving disk space by modifying the file to save only the parameters of interest (i.e, N0:gm). More information about the save command can be found in the spectre documentation or by running spectre -h save at the terminal.

Cadence APS vs XPS vs AMS

Cadence Spectre APS : Spectre Accelerated Parallel Simulator

Cadence Spectre XPS : Spectre eXtensive Partitioning Simulator

Cadence Spectre AMS Designer : Spectre AMS Designer Simulator

If you want to read the official documents about these three simulators, please visit cadence link.
You can also get a cadence tutorial file named: Spectre Circuit Simulator Reference from Cadence Support.
---

Spectre XPS is a FastSPICE circuit simulator that uses techniques like partitioning in order to simulate large, extracted netlists with 10's of millions of elements, and allowing IR drop analysis for extracted netlists.

Spectre APS is used for smaller designs and for highest accuracy circuits like: BER of an ADC, PLL jitter. It can be used without issues in transient analysis. (More discussions about APS, please email me.)

For introduction of AMS simulator, you can view ECEN 5007 course website of Prof. Hanh-Phuc Le.