capacitor consideration in switched-capacitor DACs

In the capacitor array of a switched-capacitor DAC, each capacitor can be expressed as below considering mismatch and parasitics;

where  is the parasitic capacitance related to the i-th capacitor and  is the mismatch equivalent capacitance affecting the unit capacitor. The effect of the parasitic capacitances can be considered deterministic, depending on layout inaccuracies, capacitor geometry, and wirings. On the contrary, the capacitance mismatch can be modeled as a Gaussian distribution of the unit capacitor value with a mean equal to the nominal capacitance, , and a standard deviation equal to 

where  being the Pelgrom mismatch coefficient, the unit capacitance, the area and the unit capacitance per area, respectively.

For example, if the Pelgrom mismatch coefficient is given as 0.43% um, for a 22fF unit capacitor with 3um x 3um area, the unit capacitance per area is 2.45fF/um^2 and the standard deviation is  0.02237fF.

Another important parasitic in the charge-redistribution array is the stray capacitance connected to the top-plate node of the array to a fixed voltage node. The parasitic capacitance causes a gain error in the converter characteristic but in some ADC topologies, it can also affect the converter nonlinearity.

The maximum standard deviation of the DNL in a conventional binary weighted array with single-ended input is

In order to get less than 1LSB DNL, the unit capacitor needs to be

Using the above parameters, a 10bit DAC needs to have a larger than 733fF unit capacitor to guarantee the DNL less than 1LSB.

Ref[1] mentioned that overall limitations and a suitable margin suggest using a unit capacitor in SC DACs to be larger than 40fF.

Hence, interesting research could study how the size of capacitors in DAC affects its linearity.

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[1] Design of an ultra-low power SA-ADC with medium/high resolution and speed written by Andrea Agnes, and et al. 

ADC main parameters

ADC signal-to-noise and distortion ratio (SNDR or SiNAD)

Total Harmonic Distortion(THD)

Where V2, V3,...Vn are the magnitude of harmonic distortions. Higher frequency will have less magnitude, which is less than the noise floor or is beyond the bandwidth of interest. Data sheet typically specifies to what order the harmonic distortion has been calculated. For example, up to the fifth harmonic is common. 

Signal-to-noise ratio (SNR)

ENOB

For testing ADC, a near full-scale input signal (the preferred input-tone amplitude is -0.5dBFS to -1dBFS) is applied, which avoids the situation of overdriving the quantizer. For the full-scale input, ENOB is expressed:

If the input signal is less than full-scale, like -0.5dBFS (expressed in dB related full scale), the ENOB is expressed:

Clock Jitter

High-speed high-resolution ADCs are sensitive to the quality of the clock input. To achieve superior SNR in a high-speed ADC, the RMS clock jitter must be carefully considered, based on the requirements of the applications' input frequency. 

Clock jitter limited SNR can be plotted against the analog input frequency for various clock-jitter profiles

Faster input frequency needs smaller clock jitter to obtain the same SNR. For example, an rms clock jitter of 200fs limits an ADC's SNR performance to no better than 70dB at 250MHz. However, a 1GHz input signal would need an rms clock jitter of 50fs or better to achieve the same SNR performance of 70dB. 

SAR ADC design consideration

A typical SAR ADC consists of three components: DAC, comparator, and SAR logic. It has become a superior ADC topology with a good tradeoff between power consumption, speed, and resolution.

Many studies have been made in several aspects. The first one is related to DAC topology. There are three main structures: switched resistors network, switched current sources network, and switched capacitors network. Among them, two main categories of Switched-capacitor DACs are charging-sharing and charge-redistribution. Many scholars made efforts on proposing and discussing different types of SC architectures and switching algorithms to improve the efficiency, linearity, accuracy and power consumption.

The second one is related to comparator design. The dynamic comparator has been dominant for good power efficiency. Inverter-based and time-based comparator have been popular recently.

The third one is related to SAR logic. The switching method can be accounted for this aspect. The SAR logic also plays a role in outputting digital codes. When the CMOS processing keeps scaling, the digital power of the SAR logic becomes more dominant in the whole SAR ADC. So to find a better way of saving digital power could be a promising research direction.

In addition, people also study the non-binary search, binary search with redundancy, and calibration method to optimize the linearity, mismatch and gain error issues for the SAR ADC architecture.




The SC DAC network doesn't consume static power so it is widely used for low power applications. Another reason is that SC network can be used as S/H circuit in the sampling phase.

In terms of SC DAC, many studies have been made on capacitor array topologies and switching methods. Some parameters like ADC linearity, energy efficiency, performance, and area are used to evaluate them.

The split capacitor topology is one of them, which aims to reduce the capacitor area. However, considering the capacitor mismatch, parasitic capacitance, kT/C noise, the split capacitor topology is more sensitive to parasitic effects, a larger unit capacitor must be used and in some cases can produce even larger total area than simply binary-weighted capacitor network.

Timing characteristics of an A/D converter

Three timing terms are important in every A/D converter.

• acquisition time: it is the time needed for the input signal to be connected to the internal capacitor of the ADC and store its voltage on the internal sampling capacitor. 

• conversion time: it is the time of the ADC to complete the digitization process through several comparisons. 

• throughput rate: it is also called sampling rate. It means the maximum frequency at which A/D converter can be repeated.