RMS to Peak-to-Peak Jitter conversion

To converter between RMS and peak-to-peak random jitter, the bit-error-rate (BER) must be specified.

 

$Jitter_{P-P}=\alpha \times Jitter_{RMS}$

where $\alpha$ is determined by $\frac{1}{2}erfc(\frac{\alpha}{2\sqrt{2}})=BER$

The following table is to depict the scaling factor for different BER.

If some one wants to save a copy of the table to his or her personal computer, please click the link to download: google sheet link.

RMS noise value of comparator

The comparator offset is mean value of output normal distribution. RMS noise value is the one standard deviation of the normal distribution.

For an error rate $10^{-12}$, the input must exceed the input offset by up and down $\alpha/2$ times the RMS noise level. For example, the offset of an comparator is $3mV$. The RMS noise is $1mV$, so the high output logic level the required input voltage is $3mV + 14.069 /2 \times 1mV = 10mV$. For the low output logic level, the input must be below $-4mV$.

 

TechPaper - ANALOG IC TECHNOLOGIES FOR FUTURE WIRELESS SYSTEMS WRITTEN BY Dr. MATSUZAWA

TechPaper Series :
ANALOG IC TECHNOLOGIES FOR FUTURE WIRELESS SYSTEMS WRITTEN BY Dr. MATSUZAWA

- SNR estimation in a differential Sample and Hold circuit

SNR decreases with a decrease in signal amplitude. A larger sampling capacitance is needed to keep the same SNR at the low operating voltage. However, it results in an increase in power consumption or decrease of the signal bandwidth. Therefore, the rise of signal bandwidth with moderate SNR is promising. The increase of SNR is becoming quite tough. This issue exists now common in almost all analog circuits, like ADCs, filters, and VCOs. 

PSRR comparison in different ADC architecture

Three main ADC architecture: pipeline, SAR, sigma-delta.

Among them, pipeline ADCs are the most sensitive to power supply noise because they have the lowest power supply rejection ratio. They are followed by SAR ADCs, with sigma-delta ADCs being the least sensitive to noise on the power supply.

Noise discussion in circuit

Three main noise mechanisms are attracted most of the attention: shot, flicker, thermal noise.

The figure helps explain a lot. Thermal noise is generated by the thermal agitation of the charge carriers inside an electrical conductor at equilibrium, which happens regardless of any applied voltage (Wikipedia). In other words, a low-temperature environment could reduce the thermal noise in the circuit. So some sensitive electronic equipment such as radio telescope receivers are cooled to cryogenic temperatures to reduce thermal noise in their circuits. Thermal noise in an ideal resistor is approximately white, meaning that the power spectral density is nearly constant throughout the frequency spectrum. When limited to a finite bandwidth, thermal noise has a nearly Gaussian amplitude distribution. The valuable kT/C noise consideration is also caused by the switching resistor instead of the sampling capacitor because there is no ideal switch without on-resistance.

Short noise or Poisson noise is a type of electronic noise which can be modeled by a Poisson process (Review 6 common probability distributions). For CMOS imager design, short noise needs to be concerned, because it is associated with the particle nature of light. 

Photon noise simulation. The number of photons is increased from left to right and from top to bottom. 

Flicker noise, 1/f noise, or pink noise, is a type of electronic noise with a 1/f power spectral density. Flicker noise is often characterized by the corner frequency fc between the region dominated by the low-frequency flicker noise and the higher-frequency flat band noise. MOSFETs have a higher fc than JFETs or bipolar transistors, which is usually below 2kHz for the later.

Common resolutions in the market (camera and home theater)

Ref: https://www.projectorpeople.com/resources/resolution-guide.asp

Ref: https://en.wikipedia.org/wiki/Display_resolution

Methods to reduce 1/f noise

1. Use a larger gate area WL, which has less flicker noise. Since often the op-amp input devices dominate the noise, these should have large gate areas.

2. PMOS devices have considerably smaller values for the constant K than the NMOS ones. So PMOS transistors are preferred in the design.

3. Correlated double sampling at the opamp input may store some noise and then subtracted from the signal. This introduces a highpass filtering of the noise and suppresses it effectively at frequencies which are much lower than the sampling frequency.

4. Chopper stabilization can be used to modulate the 1/f noise out of the signal band.

Interesting Features related to ADE L

1. The best size of ADE window is 700 pixels wide by 450 pixels high.

2. The variables can be edit in place by selecting the name and click in the value field to edit it.

3. The outputs can be check or uncheck the plot and save directly from the main window.

4. VAR parameterization is a good function to help you create and use design variables just about anywhere in your simulation setup. For example, you can specify the transient analysis stop time by putting VAR("stopTime") in the appropriate field in the choosing analyses from. This will automatically create a design variable which you can change directly from the main window. Similarly, you can parameterize model files and sections, simulator options and many other things.

5. Plot refresh can allows you to control the behavior of ViVa graph windows when you re-run a simulation. If you chose to auto-plot waveforms, any modification you made to your graph windows were wiped out when you re-ran the simulation.

How many points for ADC INL/DNL Histogram Simulation

The histogram test method is to apply slow linear ramp to the ADC and derives the DNL and INL directly from a total number of occurrences of each code at the output of the ADC.

How is the ramp slope? And how many points do we need for each digital code?

For example, if the ADC sampling rate is 1MHz. So every 1us we can get one sample. The LSB is 1mV. It has a 10-bit resolution.

To get 0.01LSB measurement resolution, we need 100 samples/code.

The total simulation time is 1us * 100 * 2^10=102.4 ms.
The ramp slope is 10uV/us.

IC forums: excellent places to discuss design, simulation, layout, and measurement

• The Designer's Guide Community

• EDA board

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Additional cadence design libraries for IC design

Cadence provides many design libraries.

 

Cadence also provides "Customizing the Library Manager"

The actual method is quoted as below:

"At first, create a dummy directory with the name you want to give your combined library (kind of a kludge, but oh well).  Then edit your cds.lib and add 2 lines:

DEFINE <combinedLibName> <pathToDummyDirectoryYouCreatedAbove>

ASSIGN <combinedLibName> COMBINE <lib1> <lib2> ...

These lines need to go after all the lib1, lib2, etc. libraries are defined.

That's it.  Now when you open the Library Manager, you'll see your combined library name with a "+" sign next to it.  If you click on the combined library name, you'll see all the cells in all the libraries combined.  If you click the "+" sign, you can still access the libraries individually as usual. "

Matlab toolbox for IC design

• CSATOOL to help design a switched-capacitor DAC for an SAR ADC

CSATool

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Open-source Online Tools

• Programming online for verilog/systemverilog/python/c++

EDA playground

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• Table Online Creator for LaTex/HTML/MARKDOWN

Table Generator

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• Math Equation Online Creator for HTML

MathURL

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• Free Photo Cloud Storage (html code can be embedded in Blogger)

Yahoo Flickr

capacitor consideration in switched-capacitor DACs

In the capacitor array of a switched-capacitor DAC, each capacitor can be expressed as below considering mismatch and parasitics;

where  is the parasitic capacitance related to the i-th capacitor and  is the mismatch equivalent capacitance affecting the unit capacitor. The effect of the parasitic capacitances can be considered deterministic, depending on layout inaccuracies, capacitor geometry, and wirings. On the contrary, the capacitance mismatch can be modeled as a Gaussian distribution of the unit capacitor value with a mean equal to the nominal capacitance, , and a standard deviation equal to 

where  being the Pelgrom mismatch coefficient, the unit capacitance, the area and the unit capacitance per area, respectively.

For example, if the Pelgrom mismatch coefficient is given as 0.43% um, for a 22fF unit capacitor with 3um x 3um area, the unit capacitance per area is 2.45fF/um^2 and the standard deviation is  0.02237fF.

Another important parasitic in the charge-redistribution array is the stray capacitance connected to the top-plate node of the array to a fixed voltage node. The parasitic capacitance causes a gain error in the converter characteristic but in some ADC topologies, it can also affect the converter nonlinearity.

The maximum standard deviation of the DNL in a conventional binary weighted array with single-ended input is

In order to get less than 1LSB DNL, the unit capacitor needs to be

Using the above parameters, a 10bit DAC needs to have a larger than 733fF unit capacitor to guarantee the DNL less than 1LSB.

Ref[1] mentioned that overall limitations and a suitable margin suggest using a unit capacitor in SC DACs to be larger than 40fF.

Hence, interesting research could study how the size of capacitors in DAC affects its linearity.

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[1] Design of an ultra-low power SA-ADC with medium/high resolution and speed written by Andrea Agnes, and et al. 

ADC main parameters

ADC signal-to-noise and distortion ratio (SNDR or SiNAD)

Total Harmonic Distortion(THD)

Where V2, V3,...Vn are the magnitude of harmonic distortions. Higher frequency will have less magnitude, which is less than the noise floor or is beyond the bandwidth of interest. Data sheet typically specifies to what order the harmonic distortion has been calculated. For example, up to the fifth harmonic is common. 

Signal-to-noise ratio (SNR)

ENOB

For testing ADC, a near full-scale input signal (the preferred input-tone amplitude is -0.5dBFS to -1dBFS) is applied, which avoids the situation of overdriving the quantizer. For the full-scale input, ENOB is expressed:

If the input signal is less than full-scale, like -0.5dBFS (expressed in dB related full scale), the ENOB is expressed:

Clock Jitter

High-speed high-resolution ADCs are sensitive to the quality of the clock input. To achieve superior SNR in a high-speed ADC, the RMS clock jitter must be carefully considered, based on the requirements of the applications' input frequency. 

Clock jitter limited SNR can be plotted against the analog input frequency for various clock-jitter profiles

Faster input frequency needs smaller clock jitter to obtain the same SNR. For example, an rms clock jitter of 200fs limits an ADC's SNR performance to no better than 70dB at 250MHz. However, a 1GHz input signal would need an rms clock jitter of 50fs or better to achieve the same SNR performance of 70dB. 

SAR ADC design consideration

A typical SAR ADC consists of three components: DAC, comparator, and SAR logic. It has become a superior ADC topology with a good tradeoff between power consumption, speed, and resolution.

Many studies have been made in several aspects. The first one is related to DAC topology. There are three main structures: switched resistors network, switched current sources network, and switched capacitors network. Among them, two main categories of Switched-capacitor DACs are charging-sharing and charge-redistribution. Many scholars made efforts on proposing and discussing different types of SC architectures and switching algorithms to improve the efficiency, linearity, accuracy and power consumption.

The second one is related to comparator design. The dynamic comparator has been dominant for good power efficiency. Inverter-based and time-based comparator have been popular recently.

The third one is related to SAR logic. The switching method can be accounted for this aspect. The SAR logic also plays a role in outputting digital codes. When the CMOS processing keeps scaling, the digital power of the SAR logic becomes more dominant in the whole SAR ADC. So to find a better way of saving digital power could be a promising research direction.

In addition, people also study the non-binary search, binary search with redundancy, and calibration method to optimize the linearity, mismatch and gain error issues for the SAR ADC architecture.




The SC DAC network doesn't consume static power so it is widely used for low power applications. Another reason is that SC network can be used as S/H circuit in the sampling phase.

In terms of SC DAC, many studies have been made on capacitor array topologies and switching methods. Some parameters like ADC linearity, energy efficiency, performance, and area are used to evaluate them.

The split capacitor topology is one of them, which aims to reduce the capacitor area. However, considering the capacitor mismatch, parasitic capacitance, kT/C noise, the split capacitor topology is more sensitive to parasitic effects, a larger unit capacitor must be used and in some cases can produce even larger total area than simply binary-weighted capacitor network.

Charge-redistribution SAR ADC vs Charge-sharing SAR ADC

Nowadays the majority of SAR ADCs are implemented in charge-redistribution (CR) topology. Charge-sharing (CS) principle turns out to be an alternative approach.

One important distinction between CR and CS SAR architectures is the shape of the current drawn from the reference voltage. The CR SAR interacts with the reference source at each bit decision cycle, the CS SAR draws all the charge required for conversion from VREF in a single cycle and performs the charge processing passively. So CS SAR ADCs ease the requirements of the reference generation circuit.

However, the CS ADC is more susceptible to comparator and noise and offset, because the latter causes non-linearity in the ADC transfer curve. In CR ADCs, comparator offset brings only an offset in the transfer curve.

Open Loop Cascade of amplifiers

N	ωN/ω1	|AV(0)|
1	1	10000
2	64.36	100
3	236.64	21.54
4	434.98	10
5	611.16	6.31
10	1066.55	2.51
20	1184.87	1.58

For a given voltage gain, cascade structure could lower each stage gain requirement and enlarge the final amplifier's bandwidth.

Table to show noise of capacitors in room temperature

Noise of capacitor at T=300K
Capacitance (fF)	sqrt(kT/C) rms noise (uV)	peak to peak noise (uV)
1	2034.698995	13429.01337
10	643.4283177	4246.626897
20	454.9725266	3002.818676
40	321.7141588	2123.313448
50	287.7498914	1899.149283
60	262.6785107	1733.678171
100	203.4698995	1342.901337
120	185.7417562	1225.895591
150	166.1324773	1096.47435
240	131.3392554	866.8390854
1000	64.34283177	424.6626897

Table to show required settling time for a ADC with different resolutions

number of bits	0.5LSB	Time Constant (k) multiplier	Time Constant (k) multiplier
8	0.1953125%	6.2	6.9
9	0.0976563%	6.9	7.6
10	0.0488281%	7.6	8.3
11	0.0244141%	8.3	9.0
12	0.0122070%	9.0	9.7
14	0.0030518%	10.4	11.1
16	0.0007629%	11.8	12.5
18	0.0001907%	13.2	13.9
20	0.0000477%	14.6	15.2
22	0.0000119%	15.9	16.6
24	0.0000030%	17.3	18.0
		1/2 LSB settling accuracy	1/4 LSB settling accuracy

If some one needs to the excel file to save a copy in a personal computer, please use the following link to download: google sheet document

Timing characteristics of an A/D converter

Three timing terms are important in every A/D converter.

• acquisition time: it is the time needed for the input signal to be connected to the internal capacitor of the ADC and store its voltage on the internal sampling capacitor. 

• conversion time: it is the time of the ADC to complete the digitization process through several comparisons. 

• throughput rate: it is also called sampling rate. It means the maximum frequency at which A/D converter can be repeated. 

How to simulate setup time and hold time of any DFF in cadence tool

Setup time is defined as the minimum amount of time before the clock's active edge that the data must be stable for it to be latched correctly. Any violation may cause incorrect data to be captured, which is known as setup violation.

Hold time is defined as the minimum amount of time after the clock's active edge during which data must be stable. A violation in this case may cause incorrect data to be latched, which is known as a hold violation. Note that setup and hold time is measured with respect to the active clock edge only.

Many fresh engineers know the definition but they don't know how to simulate them. I wrote a tutorial summarizing previous works coming from excellent engineers. 

The tutorial discussed how to simulate the setup time and hold time of a DFF.

Tips and Tricks on Virtuoso Visualization and Analysis XL Markers by Cadence

A marker is basically a label used to attach a description to a point on the trace, and by default displays the X and Y coordinates of its intersection with the trace. With the help of markers, you can view and analyze the specific points or areas on the trace and perform further analysis. You can also use the markers to represent expressions. Markers can be of various types, such as point, vertical, horizontal, AB, delta, and so on. Let us have a quick look at the picture below to get an idea of how markers look. In this picture, the trace contains the point (M1), vertical (V1), and horizontal (H1) markers.  

Here is a list of some useful bindkeys that you can keep handy:

• M, V, H: Creates a point, vertical, and horizontal marker, respectively.
• Q: Opens the marker properties form that you can use to change the various attributes of a marker, such as label, position, intercepts, significant digits, notation, and so on.
• N, P: Moves the marker to next or previous points on the trace based on the snapping criteria selected in the Next/Prev Snap Point drop-down available in the marker properties form. The default snapping criteria is Data Point. The other available options are—Local Maxima, Local Minima, Local Max or Min, Specific Y Value, Specific X Value, Global Maxima, and Global Minima. I must say it’s really an interesting and useful feature and comes handy when you want to analyze specific values on the trace.
• Shift+D: Creates a delta marker between two or more markers: It’s interesting to note that you can mix point, vertical, horizontal marker and get delta values from a point to a line.
• D: Creates a chain of delta markers. Select a marker and wherever on the trace you press the bindkey D, you will get a marker of the selected type and a delta value between them.
• Ctrl+E:  Deletes all the markers at one go. It acts like a savior when you have lots of markers added on the graph. Moreover, if you have delta markers added on to the graph, you can hide their child labels to make the graphs look neat. 

• Drag-and-Drop

Well, it is not a new feature for graphs, but a very convenient one! It’s helpful when you want to instantly view the marker intercept values at different locations on the trace. Undoubtedly, you can also change the intercept values through the marker Properties form, but you need to perform a series of steps to do that.

• Context-Sensitive Menu

Right-click a marker and use the context-sensitive menu options to perform certain marker-specific tasks, such as change the marker properties, snap the marker to the next or previous edge, delete the marker, and so on.

• Horizontal and Vertical Marker Tables

Use these assistants to view the intercept values of all the horizontal or vertical markers added on to the graph. To open these assistants, choose Window – Assistants – Vert Marker Table or Horiz Marker Table. Alternatively, right-click anywhere on the menu bar and open these assistants from the context-sensitive menu. The one thing I like about these assistants is they act as 'one-stop shop.'

•  Special Marker (AB)

We call it an AB Marker! This is a special delta marker of type XY and helps view the dx, dy, and slope values between two points on the same or different traces. Note that a graph can contain only one AB marker. To create another pair, you need to convert the AB marker into a normal delta marker.




You can use the Markers menu any time to create and work with markers. Here are some useful tips, tricks, and shortcuts that you can use and apply to make the tasks faster and improve productivity.