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ASICedu Posts In My Own Words
I customized device symbols for using CppSim/Sue tool to run skywater sky130 process.
CppSim is an open-source, wonderful and powerful EDA tool. I like to use it for running some simulations. In order to design circuits in real PDK, I start this interesting project.
Now I listed the following symbols ready to use.
The following demo is shown to demonstrate a simple circuit simulation flow by using sue+ngspice+sky130_pdk.
Cadence QRC is the parasitic RCL (resistance, capacitance, and inductance) extraction tool which is valuable and powerful to help IC designers to complete both digital- and transistor-level circuit design and assure on-time tapeout.
Several useful tips can assure engineers to run efficiently and faultless:
Pass the LVS check before proceeding
Select the correct Setup Dir to the PDK QRC folder if RuleSet is displayed 'NONE'. (different QRC setup dir: RC, RC_type, RC_max, RC_min, etc. ) In typical, select RC_max QRC folder to get the worse case result.
Set different Temperature in Extraction option. In the PVT simulation, engineers usually are asked to run TT 27C, FF -40C, SS 125C for pre- and post-simulation. So several extraction views are generated like av_extracted_rcmax_27, av_extract_rcmax_125, av_extract_rcmax_n40.
Set Ref Node to be the correct ground PIN of the design block
Set Extraction Type to be RC or C only typically
Enter all PIN names of VDDs and Grounds to the Power Nets and Ground Nets in the Filtering option
Final Correct Window of QRC extraction
After getting the parasitic extraction cell view, check/review the parasitics in schematic view could help engineers to understand which nodes have more parasitics.
Back-annotation tool can be launched in schematic window by clicking Launch ---> Plugins ---> Parasitics. In Setup Parasitics window as below, make sure select the correct view name and cell name. Then, press OK and go to Parasitics Menu to select Show Parasitics.
The original schematic displays the summation of capacitance in each node.
Post-simulation process needs to create the 'config' view of the testbench cell and then select the extraction cell view of expected subcircuits or the whole top-level design.
In the New Configuration window, please use AMS temperate for mixed-signal circuit simulation, which means the testbench has some block in verilog/verilogams models.
In the expected checking circuit, select its extraction view. Better to update or recompute the hierarchy to proceed the simulation process.
Press Open to open the schematic editor with the config view and launch ADE L or ADE XL or ADE explorer to run the simulation.
Tips:
System design procedure for Type-II second-order ADPLL
Reading the following reference, learn how to analyze the ADPLL. There is an error in calculating the resistor of the loop filter. It was corrected in the matlab code.
For better learning and understanding the publication, I created a mindmap reference and matlab code.