System design procedure for Type-II second-order ADPLL
Reading the following reference, learn how to analyze the ADPLL. There is an error in calculating the resistor of the loop filter. It was corrected in the matlab code.
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V. Kratyuk, P. K. Hanumolu, U.-K. Moon, and K. Mayaram, “A Design Procedure for All-Digital Phase-Locked Loops Based on a Charge-Pump Phase-Locked-Loop Analogy,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 54, no. 3, pp. 247–251, Mar. 2007, doi: 10.1109/TCSII.2006.889443.
For better learning and understanding the publication, I created a mindmap reference and matlab code.
- Mindmap Reference and Matlab code: Download Link (send email to me to ask for the password)
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