Creating Device Sue Symbols for SkyWater SKY130 Process

I customized device symbols for using CppSim/Sue tool to run skywater sky130 process.

CppSim is an open-source, wonderful and powerful EDA tool. I like to use it for running some simulations. In order to design circuits in real PDK, I start this interesting project.

Now I listed the following symbols ready to use.

 

 

The following demo is shown to demonstrate a simple circuit simulation flow by using sue+ngspice+sky130_pdk.

 

Cadence QRC notes

Cadence QRC is the parasitic RCL (resistance, capacitance, and inductance) extraction tool which is valuable and powerful to help IC designers to complete both digital- and transistor-level circuit design and assure on-time tapeout.

Correct QRC Tips

Several useful tips can assure engineers to run efficiently and faultless:

1. Pass the LVS check before proceeding

   

2. Select the correct Setup Dir to the PDK QRC folder if RuleSet is displayed 'NONE'. (different QRC setup dir: RC, RC_type, RC_max, RC_min, etc. ) In typical, select RC_max QRC folder to get the worse case result.

3. Set different Temperature in Extraction option. In the PVT simulation, engineers usually are asked to run TT 27C, FF -40C, SS 125C for pre- and post-simulation. So several extraction views are generated like av_extracted_rcmax_27, av_extract_rcmax_125, av_extract_rcmax_n40.

4. Set Ref Node to be the correct ground PIN of the design block

5. Set Extraction Type to be RC or C only typically

6. Enter all PIN names of VDDs and Grounds to the Power Nets and Ground Nets in the Filtering option

 

Final Correct Window of QRC extraction

 

Parasitic back-annotation

After getting the parasitic extraction cell view, check/review the parasitics in schematic view could help engineers to understand which nodes have more parasitics.

Back-annotation tool can be launched in schematic window by clicking Launch ---> Plugins ---> Parasitics. In Setup Parasitics window as below, make sure select the correct view name and cell name. Then, press OK and go to Parasitics Menu to select Show Parasitics.

The original schematic displays the summation of capacitance in each node.

Post-simulation

Post-simulation process needs to create the 'config' view of the testbench cell and then select the extraction cell view of expected subcircuits or the whole top-level design.

In the New Configuration window, please use AMS temperate for mixed-signal circuit simulation, which means the testbench has some block in verilog/verilogams models.

In the expected checking circuit, select its extraction view. Better to update or recompute the hierarchy to proceed the simulation process.

Press Open to open the schematic editor with the config view and launch ADE L or ADE XL or ADE explorer to run the simulation.

Tips:

1. Select the design block and Press 'E' to check what is the current cell view. It should be matched to the view in the config window
2. always make sure that the word 'config' exists in the schematic editor window's name
3. update and recompute the hierarchy whenever the schematic is modified or check and saved

design procedure for ADPLL parameter determination

System design procedure for Type-II second-order ADPLL 

Reading the following reference, learn how to analyze the ADPLL. There is an error in calculating the resistor of the loop filter. It was corrected in the matlab code.

[1]

V. Kratyuk, P. K. Hanumolu, U.-K. Moon, and K. Mayaram, “A Design Procedure for All-Digital    Phase-Locked Loops Based on a Charge-Pump Phase-Locked-Loop Analogy,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 54, no. 3, pp. 247–251, Mar. 2007, doi: 10.1109/TCSII.2006.889443.

For better learning and understanding the publication, I created a mindmap reference and matlab code. 

• Mindmap Reference and Matlab code: Download Link (send email to me to ask for the password)

PFD gain calculation

 

Simulink model of Scrambler and Descrambler

Scrambler often referred as randomizer basically removes long stream of zeros and ones from the data. It is used in wireless transmitter and receiver chain. Descrambler is the reverse operation.

Link: https://wwr.lanzoui.com/iwlVxpxtk6d

Zip file is password protected. Please send an email to asic at asicedu.com for asking.

HSCPIE Files Explanation

HSPICE Major Files Explanation

Input files:

1. netlist source: filename.sp
2. initialization: hspice.ini
3. design configuration: filename.cfg

Output files:

• run status: filename.st0
• output listing: filename.lis
• graph data files

gRAPH DATA	ANALYSIS RESULT
*.tr0	transient
*.sw2	dc
*.ac1	ac

in general, you only need to know about some of these files: source file, output listing, and graph data.

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source file (.sp)

The source file contains your circuit description and all options and analysis setup.

 

For example:

Output listing(.lis)

This is one of the most important files in HSPICE as this file lists all results obtained from the simulation. This file contains (in order of listing in the file):

• HSPICE licensing information
• Listing of the circuit
• Results form the analysis of the circuit (.op, .print, .plot, .measure, .ac, and .tran in order of their appearance in the source file)

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reference: Files (columbia.edu)

charge pump non-ideal design consideration

The practical design issues in PLLs related to the charge pump block is the unbalanced large-signal operation that transforms the timing information or phase difference information to analogue quantity in voltage to control the VCO. 

Three different design considerations for PFD+CP noise performance:

- leakage current of Charge Pump: the reference spur caused by the leakage current is possibly substantial in frequency synthesizers. (If the spur level is not enough to meet the requirement, the loop bw should be further narrowed or the charge pump current should be increased. Note: reducing the division value by increasing the frequency frequency like fractional-N frequency synthesizers is very helpful to relax the charge pump design.)

- mismatches in Charge Pump: CP mismatch has two factors: one is the current mismatch, the other is the switching-on time mismatch of UP/DOWN operations. When the mismatch is given in the charge pump, it is important to reduce the turn-on time of the PFD that is equivalent to the minimum pulse width of the output to avoid the dead-zone. 

- timing mismatch in PFD: timing mismatch is inherent in PFD with the single-ended charge pump since the UP/DOWN outputs have to drive PMOS and NMOS switches. (When delay mismatch is much smaller than the turn-on time of PFD, the timing mismatch issue is less significant compared to the leakage current or the mismatch in the charge pump.)