The practical design issues in PLLs related to the charge pump block is the unbalanced large-signal operation that transforms the timing information or phase difference information to analogue quantity in voltage to control the VCO.
Three different design considerations for PFD+CP noise performance:
- leakage current of Charge Pump: the reference spur caused by the leakage current is possibly substantial in frequency synthesizers. (If the spur level is not enough to meet the requirement, the loop bw should be further narrowed or the charge pump current should be increased. Note: reducing the division value by increasing the frequency frequency like fractional-N frequency synthesizers is very helpful to relax the charge pump design.)
- mismatches in Charge Pump: CP mismatch has two factors: one is the current mismatch, the other is the switching-on time mismatch of UP/DOWN operations. When the mismatch is given in the charge pump, it is important to reduce the turn-on time of the PFD that is equivalent to the minimum pulse width of the output to avoid the dead-zone.
- timing mismatch in PFD: timing mismatch is inherent in PFD with the single-ended charge pump since the UP/DOWN outputs have to drive PMOS and NMOS switches. (When delay mismatch is much smaller than the turn-on time of PFD, the timing mismatch issue is less significant compared to the leakage current or the mismatch in the charge pump.)
