charge pump non-ideal design consideration

The practical design issues in PLLs related to the charge pump block is the unbalanced large-signal operation that transforms the timing information or phase difference information to analogue quantity in voltage to control the VCO. 

Three different design considerations for PFD+CP noise performance:

- leakage current of Charge Pump: the reference spur caused by the leakage current is possibly substantial in frequency synthesizers. (If the spur level is not enough to meet the requirement, the loop bw should be further narrowed or the charge pump current should be increased. Note: reducing the division value by increasing the frequency frequency like fractional-N frequency synthesizers is very helpful to relax the charge pump design.)

- mismatches in Charge Pump: CP mismatch has two factors: one is the current mismatch, the other is the switching-on time mismatch of UP/DOWN operations. When the mismatch is given in the charge pump, it is important to reduce the turn-on time of the PFD that is equivalent to the minimum pulse width of the output to avoid the dead-zone. 

- timing mismatch in PFD: timing mismatch is inherent in PFD with the single-ended charge pump since the UP/DOWN outputs have to drive PMOS and NMOS switches. (When delay mismatch is much smaller than the turn-on time of PFD, the timing mismatch issue is less significant compared to the leakage current or the mismatch in the charge pump.)

Different Extraction Tools

For IC design, different extraction tools can be used to generate the post-layout netlist.

• StarRC - from Synopsys
• Quantus QRC - from Cadence
• Calibre xRC - from Mentor Graphics

Noise discussion in PFD/CP

The two noise contributions in the PFD/CP:

• PFD jitter
• noise in the output current of the CP

The PFD noise will all be in the charging and discharging edges and will be independent of how long the CP is on. However, the total noise produced by the CP will be proportional to how long it is on.

Two current sources provided to loop filter by the CP: one is pull-up current and the other pull-down current. Which one is activated depends on whether the edges on the reference input lead or lag those on the feedback input signal. When edges from PFD or UP/DOWN signals occur simultaneously, both the pull up and pull down current sources will turn on for a very short period of time. From an output current perspective the pull up and pull down currents will act to cancel each other and so the effective output current is zero. (If the current is not zero, what happens?)

And both current sources will be contributing uncorrelated noise (“Uncorrelated” means that the values are independent; that is, knowing one value provides no information about the others.) to the output while they are on. Thus, it is best to characterize the noise of the PFD/CP with simultaneous edges occurring on both the reference and feedback inputs. The output should be connected to a current probe (ideal voltage source) that is biased to present the expected voltage to the output of the CP.

Using Cadence PSS+Pnoise analysis, the phase noise of the PFD/CP can be obtained. Which is the right sweep type correct: relative or absolute?

If setting the sweep type= relative, the actual sweeping frequency is f1+n*Fpss to f2+n*Fpss, where f1 and f2 are the defined sweeping range and n is the relative harmonic number, Fpss is the PSS fundamental frequency. The benefits of the relative sweep is when simulating oscillators, because you want to look at the noise skirts around the oscillator frequency, but you don't know the oscillator frequency (accurately enough) before running, so letting PSS find it itself, and doing a relative sweep makes sense.

What about absolute sweep?

Recommended operational amplifier (opamp) reference books

 Design of Low-Voltage Low-Power Operational Amplifier Cells

- Written by Ron Hogervost and Johan Huijsing

Introduction to CMOS Opamps and Comparators

- Written by Roubik Gregorian

Operational Amplifiers -Theory and Design 

- Written by Johan H. Huijsing

Analog Integrated Circuit Design 

- Written by David Johns and Ken Martin

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Wide Dynamic Range TDC 2015-TCASII Paper 8/2020

Publication Title: A_Wide_Range_42_psrms_Precision_CMOS_TDC_With_Cyclic_Interpolators_Based_on_Switched-Frequency_Ring_Oscillators

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The publication obtained a 327us measurement range with a main reference clock counter and two interpolators. The design method is based on Nutt interpolation.

The introduction was excellent to teach us to learn about the TDC background. Although TDCs are used in ADPLLs as a phase detector, the paper focused on its another application: time-of-flight applications. That means the wide-range TDC is used to measure distance with a few hundred kHz clock rate.

Personally, I really like the rest of the introduction to discuss different types of TDC. Flash type TDCs using delay lines or ring oscillators have a nonlinearity issue caused by the delay mismatch and threshold mismatch. The vernier delay line improves the TDC resolution by subtracting two delay values. However, for the same measurement range, the vernier delay TDCs need longer delay units than the flash type TDCs. And also the random jitter increases as the delay line increases. Both of them is sensitive to PVT variations.

The third type of TDC is gated ring oscillator type. It provides a 1st order noise shaping. Without reseting for every step quantization, the current phase information is retained for next quantization cycle. After differentiation, the phase error or quantization error is noise-shaped.

In addition, the pipeline, cyclic, SAR TDCs are designed with a time difference amplifiers. However, the dynamic range of them is limited.

In sum, all these TDCs can be divided to short-range and long-range. Short range TDCs could get higher resolution. However, counter-based TDCs for long range measurements needs a fast clock to obtain a good resolution.

Thus, the paper proposed a combination method (Nutt interpolation) of using a main-counter TDC dealing with long range measurement and using high resolution TDCs to measure the interpolator range. So this type of TDC can achieve both high range and high resolution.

The advantages:
1. High range + high resolution
2. The input signal is asynchronous with respect to the reference clock so the linearity of the TDC can be improved by asynchronous input scrambles all the interpolators errors.

The major design discussion of the publication focused on the ring-oscillator TDC with two frequencies to amplifier the time residue, which is called switch-frequency ring oscillator. Furthermore, a digital calibration method is introduced for radix extraction.

Two points are good to know:
1. Real circuit needs a input generator block to generate the start and stop signals
2. DFF metastability issue could happen when start/stop edge coincide with the reference clock edge. Two DFFs are used to relieve the metastability.
3. The interpolator nonlinearity doesn't mean the whole TDC is nonlinear. The static nonlinearity of the TDC depends on the relation between the reference clock and the start signal.

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By asicedu.com

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