RMS to Peak-to-Peak Jitter conversion

To converter between RMS and peak-to-peak random jitter, the bit-error-rate (BER) must be specified.

 

$Jitter_{P-P}=\alpha \times Jitter_{RMS}$

where $\alpha$ is determined by $\frac{1}{2}erfc(\frac{\alpha}{2\sqrt{2}})=BER$

The following table is to depict the scaling factor for different BER.

If some one wants to save a copy of the table to his or her personal computer, please click the link to download: google sheet link.

RMS noise value of comparator

The comparator offset is mean value of output normal distribution. RMS noise value is the one standard deviation of the normal distribution.

For an error rate $10^{-12}$, the input must exceed the input offset by up and down $\alpha/2$ times the RMS noise level. For example, the offset of an comparator is $3mV$. The RMS noise is $1mV$, so the high output logic level the required input voltage is $3mV + 14.069 /2 \times 1mV = 10mV$. For the low output logic level, the input must be below $-4mV$.

 

TechPaper - ANALOG IC TECHNOLOGIES FOR FUTURE WIRELESS SYSTEMS WRITTEN BY Dr. MATSUZAWA

TechPaper Series :
ANALOG IC TECHNOLOGIES FOR FUTURE WIRELESS SYSTEMS WRITTEN BY Dr. MATSUZAWA

- SNR estimation in a differential Sample and Hold circuit

SNR decreases with a decrease in signal amplitude. A larger sampling capacitance is needed to keep the same SNR at the low operating voltage. However, it results in an increase in power consumption or decrease of the signal bandwidth. Therefore, the rise of signal bandwidth with moderate SNR is promising. The increase of SNR is becoming quite tough. This issue exists now common in almost all analog circuits, like ADCs, filters, and VCOs. 

PSRR comparison in different ADC architecture

Three main ADC architecture: pipeline, SAR, sigma-delta.

Among them, pipeline ADCs are the most sensitive to power supply noise because they have the lowest power supply rejection ratio. They are followed by SAR ADCs, with sigma-delta ADCs being the least sensitive to noise on the power supply.

Noise discussion in circuit

Three main noise mechanisms are attracted most of the attention: shot, flicker, thermal noise.

The figure helps explain a lot. Thermal noise is generated by the thermal agitation of the charge carriers inside an electrical conductor at equilibrium, which happens regardless of any applied voltage (Wikipedia). In other words, a low-temperature environment could reduce the thermal noise in the circuit. So some sensitive electronic equipment such as radio telescope receivers are cooled to cryogenic temperatures to reduce thermal noise in their circuits. Thermal noise in an ideal resistor is approximately white, meaning that the power spectral density is nearly constant throughout the frequency spectrum. When limited to a finite bandwidth, thermal noise has a nearly Gaussian amplitude distribution. The valuable kT/C noise consideration is also caused by the switching resistor instead of the sampling capacitor because there is no ideal switch without on-resistance.

Short noise or Poisson noise is a type of electronic noise which can be modeled by a Poisson process (Review 6 common probability distributions). For CMOS imager design, short noise needs to be concerned, because it is associated with the particle nature of light. 

Photon noise simulation. The number of photons is increased from left to right and from top to bottom. 

Flicker noise, 1/f noise, or pink noise, is a type of electronic noise with a 1/f power spectral density. Flicker noise is often characterized by the corner frequency fc between the region dominated by the low-frequency flicker noise and the higher-frequency flat band noise. MOSFETs have a higher fc than JFETs or bipolar transistors, which is usually below 2kHz for the later.

Common resolutions in the market (camera and home theater)

Ref: https://www.projectorpeople.com/resources/resolution-guide.asp

Ref: https://en.wikipedia.org/wiki/Display_resolution

Methods to reduce 1/f noise

1. Use a larger gate area WL, which has less flicker noise. Since often the op-amp input devices dominate the noise, these should have large gate areas.

2. PMOS devices have considerably smaller values for the constant K than the NMOS ones. So PMOS transistors are preferred in the design.

3. Correlated double sampling at the opamp input may store some noise and then subtracted from the signal. This introduces a highpass filtering of the noise and suppresses it effectively at frequencies which are much lower than the sampling frequency.

4. Chopper stabilization can be used to modulate the 1/f noise out of the signal band.

Interesting Features related to ADE L

1. The best size of ADE window is 700 pixels wide by 450 pixels high.

2. The variables can be edit in place by selecting the name and click in the value field to edit it.

3. The outputs can be check or uncheck the plot and save directly from the main window.

4. VAR parameterization is a good function to help you create and use design variables just about anywhere in your simulation setup. For example, you can specify the transient analysis stop time by putting VAR("stopTime") in the appropriate field in the choosing analyses from. This will automatically create a design variable which you can change directly from the main window. Similarly, you can parameterize model files and sections, simulator options and many other things.

5. Plot refresh can allows you to control the behavior of ViVa graph windows when you re-run a simulation. If you chose to auto-plot waveforms, any modification you made to your graph windows were wiped out when you re-ran the simulation.